With higher levels of integrated circuits on semiconductor chips, such as silicon, and the need exists for faster transistors in these circuits which can be accomplished by substantially reducing and even eliminating leakage between semiconductor devices in the integrated circuit and/or preventing the formation of parasitic transistors. For example, with trench isolation, an integrated circuit with field effect transistors (FETs), having each of their gates insulated from the silicon body by a gate oxide and positioned between a source and drain in the silicon, must be fabricated to either minimize or eliminate any parasitic edge or corner transistors at the interface of the FET region and the trench at the cross over of the gate electrode. FETs in such integrated circuits without parasitic edge transistors perform at faster switching speed and without the potential of latchup.
Higher levels of integration requires increasing numbers of transistors isolated from each other in essentially the same amount of silicon real estate as lower levels of integration. Trench isolation, in contrast to recessed oxidation isolation, commonly know as LOCOS, is the formation of thin, vertical grooves in the silicon so that the amount of silicon real estate is minimized, thereby leaving more silicon for the semiconductor devices and passive devices. Trenches normally are fabricated by anisotropically etching with a plasma gas(es) to which the silicon is selective to create substantially parallel walls or an U-shape groove deep in the silicon. If desired, V-shaped grooves can be formed by preferential wet etching of the (110) crystal plane of a {100} silicon wafer. Both types of trenches are filled with an insulating material, preferably an oxide of silicon. The walls of the etched silicon can be thermally oxidized prior to filling the trench, if so desired.
Although trench isolation saves silicon for more semiconductor devices and passive devices, this isolation technique produces parasitic transistors due to diffusion of the source and drain impurities of the FET at the edges of the trench. These parasitic transistors are detrimental to the integrated circuit for at least two reasons. They increase the OFF current of the FETs, and they turn on at a lower voltage than the FETs and create a "subthreshold kink" in the current-voltage (I.sub.D -V.sub.G) characteristic curve. As the FETs are designed with smaller and smaller dimensions for higher levels of integration, the applied voltage to the FET is being lowered and the detrimental influence of the parasitic edge transistor on the operation of integrated circuit becomes even greater. One technique for reducing parasitic edge transistors is to round the edges at the top of the groove opening which is filled with insulation and to provide a gate insulation of any potential parasitic transistor which will be thicker than the gate insulation of the FET.
In addition to trying to prevent leakage and/or the formation of parasitic transistors, it difficult to deposit the insulating material into the grooves so that the grooves are completely and uniformly filled in forming the trenches. In addition, when the depth of the grooves are increased, they are more difficult to fill, especially when the aspect ratio of depth to width is 2 to 1 or greater. In using chemical vapor deposition (CVD) to fill the grooves to form the trenches with silicon containing source gases, especially a source gas, such as silane which forms nonconformal silicon oxide, care must be taken during deposition so that the deposited material does not grow shoulders at the top of the grooves which may eventually close off before the bottom of the grooves are filled.